In 1989, the CAD and SoC Design Laboratory(CSDL) was established by Professor Younghwan Kim. The main research topics in the CSDL are SoC (System-on-a-Chip) design, hardware/software codesign, low power design, design methodology, image processing. Recently, we are focusing on physical design optimization (3D-IC PDN, detailed routing and detailed placement), and deep-learning hardware accelerator design.
The Professor Seokhyeong Kang who received master’s degree in 2001 at CSDL joined to our new advisor in 2017. Currently we are looking for talented students who would like to work with us on designing state-of-the-art SoC and CAD solution. Candidates with experience or interest in one or more of the following areas will be considered seriously.If you’re interested, please email Seokhyeong Kang(shkang@postech.ac.kr).